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At least 2 years of ASIC design experience (gate array or standard cell) is required. At least one year of this experience should be based on VHDL or Verilog design and/or verification. Test (full/partial scan/BIST) experience desirable. Excellent verbal and written presentation/ communication skills are mandatory. Ability to multiplex many issues, set priorities and have a helpful/caring attitude towards clients and desire to help clients explore new technology is essential for success in the job.

A successful candidate will design and implement ASICs and FPGAs using VHDL/Verilog, logic synthesis and simulation. He/she will develop reusable modules and IP for industry standard applications. As part of the design team, you may be involved in training clients and provide final design follow-up support. Requires BSEE/MSEE with experience in ASIC design and developing ASIC release processes and methods.

Experience with VHDL/Verilog, Synopsys or other design or logic synthesis tools, a plus. Must understand hardware development process.

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