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The successful candidate will be responsible for ASIC verification efforts on client projects. Will design and implement efficiency layers spanning the test bench simulation environment to the high-level user interface. He/she must be able to master complex specifications, understand intricate data flows and event-sequences. He/she will develop reusable verification macros and build platform tools used by verification engineers using C/C++ as well as develop specifications and suites of tools. Will also be responsible for providing technical guidance and consultation to design and verification engineers in the detailed implementation of the verification effort. Requires BSEE/MSEE with design/verification experience and/or experience developing ASIC release processes and methods. Must be proficient with Perl, C/C++ programming and have experience with VHDL/Verilog/Vera.

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